This application claims priority to Korean Patent Application No. 2004-64063 filed on Aug. 13, 2004 in the Korean Intellectual Property Office (KIPO), the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an intermediate frequency receiver with magnitude and phase calibration of intermediate frequency signals for improved image rejection ratio.
2. Description of the Related Art
With rapid development of wireless communication and IC design technology, the design and implementation of radio frequency (RF) transceiver systems have evolved greatly. The RF transceiver system is desired to be designed with high degree of integration, a small-sized chip, and low power consumption. Such RF transceiver systems may be mainly categorized into a zero-IF (Intermediate Frequency) architecture and a low-IF architecture.
The low-IF architecture uses an intermediate frequency that is about 1 to 2 times lower than a signal bandwidth. The low-IF architecture is less influenced by DC offset and 1/f noise than the zero-IF architecture. However, in the low-IF receiver architecture, the desired RF signal may be influenced by the image signal having a frequency very close to the desired RF signal. Thus, the image signal should be removed for maintaining receiver performance.
Generally, two mechanisms for image rejection in a low-IF receiver are referred to as the “Hartely, Weaver image-rejection architecture” and the “polyphase image rejection filter”. However, adequate image rejection is still difficult to achieve from IQ gain mismatch and phase mismatch.
Thus, a LMS (Least Mean Square) algorithm and a technique for calibrating gain and phase using a digital compensation algorithm have been proposed. The LMS algorithm is disclosed in IEEE journal of solid-state circuits, Vol. 38, No. 2, February 2003, entitled “A 2-GHz CMOS Image-Rejection Receiver with LMS Calibration” by Lawrence Der and Behzad Razavi. The technique for calibrating gain and phase using a digital compensation algorithm is disclosed in Microwave Symposium Digest, and 2002 IEEE MTT-S International, Vol. 2, pp. 792-802, June 2002, entitled “Architecture and Algorithm for High Precision Image Rejection and Spurious Rejection Mixers Using Digital Compensation” by Youngjin Kim et al.
The conventional calibration circuit employing the LMS algorithm includes three 11-bit DACs, and the conventional calibration circuit employing the digital compensation algorithm includes two 12-bit ADC. Accordingly, such conventional calibration circuits occupy relatively large chip space and have increased power consumption. In a conventional calibrating circuit and method for improving image rejection ratio IRR, a digital unit performs a calibrating operation using a high resolution ADC or DAC. Therefore, the digital unit occupies a relatively large chip space and has increased power consumption.
U.S. Pat. No. 6,137,999 to Lovelace et al. discloses an image reject transceiver, but teaches only adjustment of an intermediate frequency signal generated after transmission from a mixer. U.S. Pat. No. 6,560,449 to Liu discloses image-rejection I/Q demodulators, but teaches only adjustment of local oscillator signals generated before transmission through a mixer. U.S. Patent Application No. 2004/0002323 to Zheng discloses an image rejection down conversion system, but teaches only adjustment of intermediate frequency signals generated after transmission from mixers.